Device and Method for Configuring Input/Output Pads

ABSTRACT

A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits.

FIELD OF THE INVENTION

The present invention relates to a device and to a method forconfiguring Input/Output (IO) pads.

BACKGROUND OF THE INVENTION

Integrated circuits include multiple input/output (IO) pads that areused to convey signals to the integrated circuit and from the integratedcircuit. Some IO pad circuits are used only to receive signals, other IOpad circuits are used to output signals and some IO pad circuits areused to receive signals and to output signals.

Usually, the number of signals that should be exchanged between theintegrated circuit and its environment well exceeds the number of IO padcircuits, thus time division multiplexing is applied.

IO pads are required to change their characteristics (such as impedance,drive strength, slew rate and the like) in response to the functionsthat they are currently executing. In order to support these relativelyrapid IO characteristic changes configurable IO pad circuits weredeveloped.

Usually, a configurable IO pad circuit includes a control/configurationcircuit and an IO pad. For simplicity of explanation thecontrol/configuration circuits are referred to as control circuits.

The number of IO pad circuit configuration control signals is relativelylarge and can exceed ten. Multiple IO pad circuit configuration controlsignals form a multi-bit IO pad circuit configuration control word.

These signals are usually routed in dedicated IO channels that arerelatively area-consuming and their design is relatively time consumingand complex. In a typical base-band integrated circuit the IO channelscan require a total area of about two square millimeters.

FIG. 1 illustrates a lower part of an integrated circuit 5. IO padcircuits 6 surround IO channels 7 that in turn surround a portion 8 ofthe integrated circuit 5 that is not physically connected to theintegrated circuit environment. Portion 8 can include one or moretransistor based component such as but not limited to processors, memoryunits, logic and the like.

A more detailed illustration of configurable IO pad circuits and methodsfor configuring IO pad circuits are also illustrated in U.S. Pat. No.6,851,079 of Hergott titled “JTAG test access port controller used tocontrol input/output pad functionality”, and U.S. patent applicationserial number 2004/0117698 of Tran et al., titled “Programmablemanagement IO pads for an integrated circuit”, which are incorporatedherein by reference.

FIG. 2 illustrates a prior art integrated circuit 9 that includes IO padcircuits. An IO pad circuit includes an IO pad (POUT) 28 and an IO padcontrol circuit (PCNT) 29 that can receive information from JTAGcompliant boundary scan cells. A PCNT 29 receives IO pad circuitconfiguration signals (denoted “control”) from core 11. The IO padcircuit configuration signals are routed vian IO channels, such as IOchannels 7 of FIG. 1.

JTAG (also known as IEEE standard 1149.1) was designed in order to testintegrated circuits. The IEEE standard 1149.1 defines a test access port(TAP) that may be used to access internal components of an integratedcircuit. The TAP includes a boundary scan register 30, a one-bit longbypass register 12, an instruction register 18, a TAP controller 20, andan optional user defined data register 14.

A TAP receives various signals including a clock signal TCK, a test datainput signal TDI, a test mode select signal TMS. The TAP can output atest data output signal TDO. Various control signals provided by the TAPcontroller 20, especially in response to TMS signals, select a pathbetween the TDI and TDO ports of the TAP.

The instruction register 18 forms an instruction path while each of theboundary scan register 30, bypass register 12 and the optional userdefined data register 14 defines a data path. Each data path andinstruction path can be regarded as an internal test path of the TAP.

The TAP controller 20 is a state machine that can apply many stages,including various IEEE standard 1149.1 mandatory states. These mandatorystates are controlled by the TMS signal. FIG. 4 illustrates the multiplestates of the TAP controller 20: Test logic reset 40, run-test/idle 41,select DR scan 42, capture DR 43, shift DR 44, exit1 DR 45, pause DR 46,exit2 DR 47, update DR 48, select IR scan 52, capture IR 53, shift IR54, exit1 IR 55, pause IR 56, exit2 IR 57 and update IR 58. The stagesare illustrates as boxes that are linked to each other by arrows. Thearrows are accompanied by digits (either 0 or 1) that illustrate thevalue of the TMS signal. These stages are well known in the art andrequire no further explanation.

Generally, the TAP controller 20 sends control signals that allow toinput information into selected data and instruction paths, to retrieveinformation from said paths and to serially propagate (shift)information along data and instruction paths.

The boundary scan register 30 includes multiple boundary scan cells(denoted BSC) 32. Some BSCs are connected to input pad circuits 26 whileothers are connected, via PCNTs 29 to IO pad 28. Especially, each IO pad28 is connected to a PCNT 29 that can receive configuration signals(denoted “control”) from core 11, data from certain BSCs and enablesignals from other BSCs 32. A pair of BSCs are allocated for each IO pad28.

FIG. 3 illustrates a prior art integrated circuit 9′ that includes IOpads 28, a TAP and a control selection multiplexer 23. For simplicity ofexplanation some registers were omitted.

Integrated circuit 9′ differs from integrated circuit 9 by including acontrol selection multiplexer 23 that can send to PCNTs 29 either (i) IOpad circuit configuration signals provided by core 11 or (ii)configuration signals generated by the TAP. The latter is usuallyprovided during test mode while the former is provided during normalmode. A PCNT 29 can receive enable signals from one BSC, a data signalfrom another BSC and IO pad circuit configuration signals from controlmultiplexer 23.

The IO pad circuit configuration signals usually include multiplesignals thus requiring complex and area consuming IO channels.

There is a growing need to provide efficient devices and methods forprogramming IO pad circuits.

SUMMARY OF THE PRESENT INVENTION

A device and a method for programming IO pads, as described in theaccompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 illustrates a lower part of an integrated circuit;

FIG. 2 illustrates a prior art integrated circuit that includes IO padcircuits that can receive information from JTAG compliant boundary scancells, and receive IO pad configuration signals from a core;

FIG. 3 illustrates a prior art integrated circuit that includes IO padcircuits, a TAP and a control selection multiplexer;

FIG. 4 illustrates the multiple states of the TAP controller;

FIG. 5 illustrates a device according to an embodiment of the invention;

FIG. 6 illustrates a device according to another embodiment of theinvention; and

FIG. 7 illustrates a method for configuring IO pads, according to anembodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A device that uses a boundary scan register to provide data andconfiguration information to IO pad circuits. Typically, configurationinformation includes multiple bits. A boundary scan register is used toprovide configuration information during multiple write sessions.

During each write session multiple IO pad circuits receive a certain padconfiguration bit. In addition, the same boundary scan register is usedto convey data. One or more selection signals select the destination ofthe data an/or the configuration bits.

A method for configuring IO pads is provided. The method includesdetermining a current configuration of multiple IO pads of an integratedcircuit, generating multiple boundary scan register words that includeconfiguration information, and repeating the stage of serially writing acertain boundary scan register word to a boundary scan register andoutputting the boundary scan register word to multiple IO pad controlcircuits. The repetition ends once a predefined amount of differentboundary scan words is written.

Conveniently, the generating includes converting multiple configurationinformation words to multiple boundary scan register words.Conveniently, each IO pad control circuit includes multiple controlpaths and the writing includes sending a boundary scan register bit to aselected control path. Conveniently, each IO pad control circuitincludes multiple latches and the writing includes sending a boundaryscan register bit to a selected latch out of the multiple latches.

Conveniently, the method further includes providing data to the IO padcircuits via the boundary scan register. Conveniently, the providingincludes sending data via one data path within an IO pad control circuitand whereas the writing includes sending a boundary register bit via acontrol path out of multiple control paths within an IO pad controlcircuit.

Conveniently, the method also includes comparing a current boundary scanword to a corresponding previously written boundary scan word anddetermining, in response to the comparison, whether to write the currentboundary scan word.

A device is provided. The device includes a core, a boundary scanregister, a TAP controller, multiple IO pad circuits and a controlcircuit. The control circuit is adapted to determine a currentconfiguration of the IO pad circuits, to generate multiple boundary scanregister words that include configuration information; and to control arepetition of: (i) writing a certain boundary scan register word to theboundary scan register and (ii) outputting the boundary scan registerword to multiple IO pad control circuits.

Conveniently, the control circuit is adapted to convert multipleconfiguration information words to multiple boundary scan registerwords. Conveniently, each IO pad control circuit includes multiplecontrol paths and a selection circuit adapted to send a boundary scanregister bit to a selected control path. Conveniently, each control pathincludes a latch.

Conveniently, an IO pad control circuit also includes a data path forproviding data to an IO pad circuit. Conveniently, the device is adaptedto send data via one data path within an IO pad control circuit and tosend a boundary register bit via a control path out of multiple controlpaths within an IO pad control circuit.

Conveniently, the device is adapted to compare a current boundary scanword to a corresponding previously written boundary scan word anddetermine, in response to the comparison, whether to write the currentboundary scan word.

FIG. 5 illustrates a device 10 according to an embodiment of theinvention.

Device 10 can be an integrated circuit or can include one or moreintegrated circuits. It can be a mobile phone, a computer, a personaldata accessory and the like.

FIG. 5 illustrates a limited amount of boundary scan cells and IO pads,as well as only few components of device 10. It is noted that the amountof boundary scan cells usually exceeds the amount illustrated in FIG. 5,that device 10 usually includes multiple components (such as but notlimited to memory units, additional cores, logic, peripherals and thelike).

Device 10 includes a core 11, boundary scan register 30, two pad controlcircuits (PCC1 101 and PCC2 201), two IO pads 151 and 152, bypassregister 12, instruction register 18, TAP controller 20, multiplexer 22and an optional user defined data register 14. The TAP receives TDI, TMSand TCK signals (generated by control circuit 19) and outputs, viamultiplexer 22, a TDO signal. Boundary scan register 30 includesboundary scan cells 321-324. Boundary scan cells 323 and 324 areconnected to input pads 26. Boundary scan cells 321 and 322 areconnected to IO pads 151 and 152 accordingly, via pad control circuits101 and 201.

It is assumed that K bits are required to configure a single IO padcircuit. It is also assumed that the device 11 includes J IO pads (suchas PO1-POJ 150 of FIG. 8), including IO pads 151 and 152. In order toconfigure the J IO pads K write sessions are required. It is assumedthat index k represents the write session and that k ranges between 1and K. The k'th write sequence includes serially loading a k'th boundaryscan register word (which is J-bit long) to the J boundary scan cellsthat form boundary scan register 30. Once the boundary scan register isloaded (within BSC1-BSCJ 32 of FIG. 8) the J boundary scan cells outputsthe k'th boundary scan register word to J pad control circuits (such asPCC1-PCCJ 100 of FIG. 8). Conveniently, each pad control circuit (suchas PCC1 101) includes a de-multiplexer (such as de-multiplexer 111).Each de-multiplexer also receives a control_select signal that indicateswhere to store the received bit. These bits are then used to configurethe J IO pads.

The boundary scan register words are written to the boundary scanregister 30 via TDI input. It is noted that signals TDI, TMS, TCK can beprovided by control circuit 19, another component of core 11 or by oneor more components of an integrated circuit or by an external testingcircuit.

The first IO pad control circuit 111 is connected to PO1 151. The secondIO pad circuit 201 is connected to PO2 152.

The first pad control circuit 101 includes de-multiplexer 111 andmultiple (K+1) latches L11-LD1 121-133. K latches L11-L1K 121-132 areused to store configuration bits while LD1 133 stores data.De-multiplexer 111 receives a control_select signal from core 11 and inresponse determines to which latch (out of L11-L1K 121-132) to send dataor a configuration bit received from boundary scan cell 321. The contentof latches L11-L1K 121-132 determine the configuration of IO pad 151.

The second pad control circuit 201 includes de-multiplexer 211 andmultiple (K+1) latches L21-LD2 221-233. K latches L21-L2K 221-232 areused to store configuration bits while LD2 233 stores data.De-multiplexer 211 receives a control_select signal from core 11 and inresponse determines to which latch (out of L21-L2K 221-232) to send dataor a configuration bit received from boundary scan cell 322. The contentof latches L21-L2K 221-232 determine the configuration of IO pad 152.

FIG. 6 illustrates a device 10′ according to an embodiment of theinvention. Device 10′ of FIG. 6 differs from device 10 of FIG. 5 byincluding a data path that does not include data latches. Instead ofproviding data via de-multiplexers 111 and 211 to latches L1D 133 andL2D 233 to IO pads 151 and 152, the data is sent from de-multiplexers111 and 211 to IO pads 151 and 152

According to an embodiment of the invention device 11 (or device 10′)can perform K writing sessions whenever the IO pads need to beconfigured. According to an embodiment of the invention device 11 (ordevice 11′) can perform fewer writing cycles, if at least one currentboundary scan register word equals the corresponding last writtenboundary scan register word.

FIG. 7 illustrates a method 400 for configuring IO pads, according to anembodiment of the invention. FIG. 8 illustrates the relationship betweenconfiguration words and boundary scan words, as well as writing andreading stages of a boundary scan register word, according to anembodiment of the invention. For simplicity of explanation FIG. 8 onlyillustrates the first, second and Jth configuration words as well as thefirst, second and K'th boundary scan register words. For clarity ofexplanation a writing process of a k'th boundary scan register 355 isillustrated. It is noted that a similar process is applied whenever aboundary scan word is written.

Method 400 starts by stage 410 of determining a current configuration ofmultiple IO pads of an integrated circuit. The determination can beresponsive to a currently implemented function of the IO pads. Stage 410may include generating multiple (for example J) configurationinformation words that determine the configuration of the J IO pads. Itis assumed that the j'th IO configuration word includes K bits anddetermines the configuration of the j'th IO pad. Referring to theexample set forth in FIG. 8, configuration words 341-349 are generated.Each configuration information word includes K bits.

Stage 410 is followed by stage 420 of generating multiple boundary scanregister words. Each boundary scan register word may include multipleconfiguration bits that are should affect multiple IO pads. For example,the k'th boundary scan register word can include the k'th bits of theconfiguration information words.

Referring to the example set forth in FIG. 8, K boundary scan registerwords 351-362 are generated. The first boundary scan register word 351includes the first bit of each of the J configuration words 341-349. Thesecond boundary scan register word 352 includes the second bit of eachof the J configuration words 341-349. The K'th boundary scan registerword 362 includes the K'th bit of each of the J IO pad configurationwords 341-349.

Stage 420 is followed by stages 430, 440, 450 and 460 that cause themultiple boundary scan register words to be serially written to theboundary scan register and to be written to multiple IO pad controlcircuits that are connected in parallel to multiple boundary scan cellsof the boundary scan register.

Referring to the example set forth in FIG. 8, a k'th boundary scanregister word 355 is serially written (using TDI signals) to the Jboundary scan cells (BSC1-BSCJ, collectively denoted 32) that form theboundary scan register 30. Once the whole boundary scan word is writtenthe boundary scan cells BSC1-BSCJ (collectively denoted 32) sendmultiple boundary scan register bits to pad control circuits PCC1-PCCJ(collectively denoted 100) that are connected to these boundary scancells. Each pad control circuit sends a configuration information wordto the corresponding IO pad (PO1-POJ, collectively denoted 150). Thefirst IO pad P01 receives the first configuration word 341, the secondIO pad PO2 receives the second configuration word 342, and the K′th IOpad POK receives the K′th configuration word 349.

Stage 430 includes setting index k to one (k=1).

Stage 430 is followed by stage 440 of serially writing the k'th boundaryscan register word to the boundary scan register, and then outputtingmultiple boundary scan register bits to multiple IO pad controlcircuits. Conveniently, stage 440 includes receiving the bits byde-multiplexers and selecting a selected latch to receive the bits.

Stage 440 can include stage 442 of comparing a current boundary scanword to a corresponding previously written boundary scan word and stage444 of determining, in response to the comparison, whether to write thecurrent boundary scan word.

Stage 440 is followed by stage 450 of incrementing k (k=k+1). Stage 450is followed by stage 460 of checking if k is greater than K. if theanswer is negative then stage 460 is followed by stage 430, else stage460 is followed by stage 470 of configuring the IO pads according to theConfiguration information provided to the IO pad control circuits.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

1. A method for configuring IO pads of an integrated circuit, the methodcomprises determining a current configuration of multiple IO pads;generating multiple boundary scan register words that compriseconfiguration information; and repeating the stage of serially writing acertain boundary scan register word to a boundary scan register andoutputting the boundary scan register word to multiple IO pad controlcircuits; wherein a k'th boundary scan register word comprises k'th bitsof multiple configuration information words; wherein the configurationinformation comprises IO drive strength information.
 2. The methodaccording to claim 1 whereas the generating IO comprises convertingmultiple configuration information words to the multiple boundary scanregister words.
 3. The method according to any claim 1 whereas each IOpad control circuit comprises multiple control paths and whereas thewriting comprises sending a boundary scan register bit to a selectedcontrol path.
 4. The method according to claim 3 whereas each IO padcontrol circuit comprises multiple latches and whereas the writingcomprises sending a boundary scan register bit to a selected latch outof the multiple latches.
 5. The method according to a claim 1 furthercomprising providing data to the IO pads via the boundary scan register.6. The method according to claim 5 whereas the providing comprisessending data via one data path within an IO pad control circuit andwhereas the writing comprises sending a boundary register bit via acontrol path out of multiple control paths within an IO pad controlcircuit.
 7. The method according to any claim 1 further comprisingcomparing a current boundary scan word to a corresponding previouslywritten boundary scan word and determining, in response to thecomparison, whether to write the current boundary scan word.
 8. Adevice, comprising: a core, coupled to a boundary scan registers; a TAPcontrollers; and multiple IO pads; a control circuit adapted todetermine a current configuration of the IO pad circuits, to generatemultiple boundary scan register words that comprise Configurationinformation; and to control a repetition of writing a certain boundaryscan register word to the boundary scan register and outputting theboundary scan register word to multiple IO pad control circuits; whereina k'th boundary scan register word comprises k'th bits of multipleconfiguration information words; wherein the configuration informationcomprises IO drive strength information.
 9. The device according toclaim 8 whereas the control circuit is adapted to convert multipleConfiguration information words to the multiple boundary scan registerwords.
 10. The device according to any claim 8 whereas each IO padcontrol circuit comprises multiple control paths and a selection circuitadapted to send a boundary scan register bit to a selected control path.11. The device according to claim 10 whereas each control path comprisesa latch.
 12. The device according to any claim 8 further comprising adata path for providing data to an IO pad circuit.
 13. The deviceaccording to claim 12 further adapted to send data via one data pathwithin an IO pad control circuit and to send a boundary register bit viaa control path out of multiple control paths within an IO pad controlcircuit.
 14. The device according to claim 8 whereas the control circuita is adapted to compare a current boundary scan word to a correspondingpreviously written boundary scan word and determine, in response to thecomparison, whether to write the current boundary scan word.
 15. Themethod according to claim 2 whereas each IO pad control circuitcomprises multiple control paths and whereas the writing comprisessending a boundary scan register bit to a selected control path.
 16. Themethod according to claim 2 further comprising providing data to the IOpads via the boundary scan register.
 17. The method according to claim 2further comprising comparing a current boundary scan word to acorresponding previously written boundary scan word and determining, inresponse to the comparison, whether to write the current boundary scanword.
 18. The method according to claim 3 further comprising providingdata to the pads via the boundary scan register.
 19. The deviceaccording to claim 9 whereas each IO pad control circuit comprisesmultiple control paths and a selection circuit adapted to send aboundary scan register bit to a selected control path.
 20. The deviceaccording to claim 9 further comprising a data path for providing datato an IO pad circuit.